diff -urN oldtree/arch/i386/Kconfig newtree/arch/i386/Kconfig
--- oldtree/arch/i386/Kconfig 2006-06-07 15:35:00.025013250 +0000
+++ newtree/arch/i386/Kconfig 2006-06-08 20:24:21.970812500 +0000
@@ -426,6 +426,43 @@
source "drivers/firmware/Kconfig"
choice
+ depends on EXPERIMENTAL && !X86_PAE
+ prompt "Memory split"
+ default VMSPLIT_3G
+ help
+ Select the desired split between kernel and user memory.
+
+ If the address range available to the kernel is less than the
+ physical memory installed, the remaining memory will be available
+ as "high memory". Accessing high memory is a little more costly
+ than low memory, as it needs to be mapped into the kernel first.
+ Note that increasing the kernel address space limits the range
+ available to user programs, making the address space there
+ tighter. Selecting anything other than the default 3G/1G split
+ will also likely make your kernel incompatible with binary-only
+ kernel modules.
+
+ If you are not absolutely sure what you are doing, leave this
+ option alone!
+
+ config VMSPLIT_3G
+ bool "3G/1G user/kernel split"
+ config VMSPLIT_3G_OPT
+ bool "3G/1G user/kernel split (for full 1G low memory)"
+ config VMSPLIT_2G
+ bool "2G/2G user/kernel split"
+ config VMSPLIT_1G
+ bool "1G/3G user/kernel split"
+endchoice
+
+config PAGE_OFFSET
+ hex
+ default 0xB0000000 if VMSPLIT_3G_OPT
+ default 0x78000000 if VMSPLIT_2G
+ default 0x40000000 if VMSPLIT_1G
+ default 0xC0000000
+
+choice
prompt "High Memory Support"
default NOHIGHMEM
diff -urN oldtree/arch/i386/kernel/cpu/cpufreq/Kconfig newtree/arch/i386/kernel/cpu/cpufreq/Kconfig
--- oldtree/arch/i386/kernel/cpu/cpufreq/Kconfig 2006-06-07 15:32:34.000000000 +0000
+++ newtree/arch/i386/kernel/cpu/cpufreq/Kconfig 2006-06-08 20:24:21.986813500 +0000
@@ -107,13 +107,45 @@
config X86_SPEEDSTEP_CENTRINO
tristate "Intel Enhanced SpeedStep"
select CPU_FREQ_TABLE
- select X86_SPEEDSTEP_CENTRINO_TABLE if (!X86_SPEEDSTEP_CENTRINO_ACPI)
+ select X86_SPEEDSTEP_CENTRINO_ACPI if (!X86_SPEEDSTEP_CENTRINO_BUILTIN || (!X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS && !X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN && !X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA ))
help
This adds the CPUFreq driver for Enhanced SpeedStep enabled
mobile CPUs. This means Intel Pentium M (Centrino) CPUs. However,
- you also need to say Y to "Use ACPI tables to decode..." below
- [which might imply enabling ACPI] if you want to use this driver
- on non-Banias CPUs.
+ you also need to say Y below to at least one of the following options:
+ - "Use ACPI tables to decode..." [which might imply enabling ACPI]
+ - "Built-in Tables for ... CPUs"
+ - "Default table"
+
+ You can also say yes to all of these options. In this configuration the
+ driver will first try to use ACPI. Then if it fails it will try to use
+ a built-in table if there is one matching the CPU. And as a last resort
+ a default table will be used.
+
+ In the last case you will also want to say yes to "Userspace control of
+ CPU frequency/voltage table" to setup the frequency/voltage operating
+ points of the CPU from the userspace. This is because de default table
+ will initially have only one operating point. This means that you will
+ need to add yourself the other control points to switch the CPU between
+ different frequencies.
+
+ For details, take a look at .
+
+ If in doubt, say N.
+
+config X86_SPEEDSTEP_CENTRINO_SYSFS
+ bool "Userspace control of CPU frequency/voltage table"
+ depends on X86_SPEEDSTEP_CENTRINO
+ depends on SYSFS
+ depends on (X86_SPEEDSTEP_CENTRINO_BUILTIN && (X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS || X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN || X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA )) || X86_SPEEDSTEP_CENTRINO_ACPI || X86_SPEEDSTEP_CENTRINO_DEFAULT
+ default y
+ help
+ Add support for user space control of the CPU frequency/voltage
+ operating points table through a sysfs interface.
+
+ If you say Y here files will be created in
+ /sys/devices/system/cpu/cpu*/cpufreq/oppoints
+ allowing reading and writing of the current table values as well as
+ adding or removing operating points.
For details, take a look at .
@@ -126,20 +158,66 @@
default y
help
Use primarily the information provided in the BIOS ACPI tables
- to determine valid CPU frequency and voltage pairings. It is
- required for the driver to work on non-Banias CPUs.
-
+ to determine valid CPU frequency and voltage pairings.
+
If in doubt, say Y.
-config X86_SPEEDSTEP_CENTRINO_TABLE
- bool "Built-in tables for Banias CPUs"
+config X86_SPEEDSTEP_CENTRINO_BUILTIN
+ bool "Built-in tables"
depends on X86_SPEEDSTEP_CENTRINO
default y
help
- Use built-in tables for Banias CPUs if ACPI encoding
- is not available.
-
- If in doubt, say N.
+ Use "hard coded" built-in tables if ACPI decoding
+ is not available.
+
+ If you say Y here you must select at least one of the CPU below.
+
+ If you are not sure of your exact CPU model you can select several CPU
+ models or all of them. The driver will only use the table that match
+ the exact CPU name and family/model/stepping numbers.
+ Selecting all the built-in tables will only add a small size overhead
+ to the kernel and an insignificant extra time to intialize the driver.
+
+ If both ACPI and built-in tables support are enabled then built-in
+ tables will be used only if ACPI table decoding fails.
+
+ If you want to force usage of built-in tables over ACPI you need to say
+ Y here and N to X86_SPEEDSTEP_CENTRINO_ACPI.
+
+ If in doubt, say Y.
+
+config X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS
+ bool "Built-in tables for Banias CPUs"
+ depends on X86_SPEEDSTEP_CENTRINO_BUILTIN
+ default y
+ help
+ Use built-in tables for Banias CPUs if ACPI encoding is not available.
+ Banias CPUs are the first generation of Pentium-M, with a 1 MB L2 cache
+ and 400 MHz FSB manufactured on 0.13 micron process.
+
+ If in doubt, say Y.
+
+config X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN
+ bool "Built-in tables for Dothan CPUs"
+ depends on X86_SPEEDSTEP_CENTRINO_BUILTIN
+ default y
+ help
+ Use built-in tables for Dothan CPUs if ACPI encoding is not available.
+ Dothan CPUs are the second generation of Pentium-M, with a 2 MB L2
+ cache and 400 MHz FSB manufactured on 90 nm process.
+
+ If in doubt, say Y.
+
+config X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA
+ bool "Built-in tables for Sonoma CPUs"
+ depends on X86_SPEEDSTEP_CENTRINO_BUILTIN
+ default y
+ help
+ Use built-in tables for Sonoma CPUs if ACPI encoding is not available.
+ Sonoma CPUs are the third generation of Pentium-M, with a 2 MB L2 cache
+ and 533 MHz FSB manufactured on 90 nm process.
+
+ If in doubt, say Y.
config X86_SPEEDSTEP_ICH
tristate "Intel Speedstep on ICH-M chipsets (ioport interface)"
diff -urN oldtree/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c newtree/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
--- oldtree/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c 2006-06-07 15:35:00.037014000 +0000
+++ newtree/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c 2006-06-08 20:24:21.994814000 +0000
@@ -53,6 +53,7 @@
CPU_DOTHAN_A1,
CPU_DOTHAN_A2,
CPU_DOTHAN_B0,
+ CPU_DOTHAN_C0,
CPU_MP4HT_D0,
CPU_MP4HT_E0,
};
@@ -62,6 +63,7 @@
[CPU_DOTHAN_A1] = { 6, 13, 1 },
[CPU_DOTHAN_A2] = { 6, 13, 2 },
[CPU_DOTHAN_B0] = { 6, 13, 6 },
+ [CPU_DOTHAN_C0] = { 6, 13, 8 },
[CPU_MP4HT_D0] = {15, 3, 4 },
[CPU_MP4HT_E0] = {15, 4, 1 },
};
@@ -72,8 +74,8 @@
const struct cpu_id *cpu_id;
const char *model_name;
unsigned max_freq; /* max clock in kHz */
-
struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
+ unsigned base_freq; /* base frequency used to convert between clock rates and MSR: FSB/4 in kHz */
};
static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
@@ -83,7 +85,9 @@
static struct cpufreq_driver centrino_driver;
-#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS
/* Computes the correct form for IA32_PERF_CTL MSR for a particular
frequency/voltage operating point; frequency in MHz, volts in mV.
@@ -131,7 +135,6 @@
{ .frequency = CPUFREQ_TABLE_END }
};
-
/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
static struct cpufreq_frequency_table banias_1200[] =
{
@@ -208,13 +211,243 @@
.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
.max_freq = (max)*1000, \
.op_points = banias_##max, \
+ .base_freq = 100000, \
}
#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS */
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN
+/* Dothan processor datasheet 30218903.pdf defines 4 voltages for each
+ frequency (VID#A through VID#D) - this macro allows us to define all
+ of these but we only use the VID#A voltages at compile time - this may
+ need some work if we want to select the voltage profile at runtime. */
+
+#define OP(mhz, mva, mvb, mvc, mvd) \
+ { \
+ .frequency = (mhz) * 1000, \
+ .index = (((mhz)/100) << 8) | ((mva - 700) / 16) \
+ }
+
+ /* Intel Pentium M processor 733 / 1.10GHz (Dothan) */
+ static struct cpufreq_frequency_table dothan_1100[] =
+{
+ OP( 600, 700, 700, 700, 700),
+ OP( 800, 748, 748, 748, 748),
+ OP( 900, 764, 764, 764, 764),
+ OP(1000, 812, 812, 812, 812),
+ OP(1100, 844, 844, 844, 844),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 710 / 1.40GHz (Dothan) */
+static struct cpufreq_frequency_table dothan_1400[] =
+{
+
+ OP( 600, 988, 988, 988, 988),
+ OP( 800, 1068, 1068, 1068, 1052),
+ OP(1000, 1148, 1148, 1132, 1116),
+ OP(1200, 1228, 1212, 1212, 1180),
+ OP(1400, 1340, 1324, 1308, 1276),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 715 / 1.50GHz (Dothan) */
+static struct cpufreq_frequency_table dothan_1500[] =
+{
+ OP( 600, 988, 988, 988, 988),
+ OP( 800, 1068, 1068, 1068, 1052),
+ OP(1000, 1148, 1148, 1132, 1116),
+ OP(1200, 1228, 1212, 1212, 1180),
+ OP(1500, 1340, 1324, 1308, 1276),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 725 / 1.60GHz (Dothan) */
+static struct cpufreq_frequency_table dothan_1600[] =
+{
+ OP( 600, 988, 988, 988, 988),
+ OP( 800, 1068, 1068, 1052, 1052),
+ OP(1000, 1132, 1132, 1116, 1116),
+ OP(1200, 1212, 1196, 1180, 1164),
+ OP(1400, 1276, 1260, 1244, 1228),
+ OP(1600, 1340, 1324, 1308, 1276),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 735 / 1.70GHz (Dothan) */
+static struct cpufreq_frequency_table dothan_1700[] =
+{
+ OP( 600, 988, 988, 988, 988),
+ OP( 800, 1052, 1052, 1052, 1052),
+ OP(1000, 1116, 1116, 1116, 1100),
+ OP(1200, 1180, 1180, 1164, 1148),
+ OP(1400, 1244, 1244, 1228, 1212),
+ OP(1700, 1340, 1324, 1308, 1276),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 745 / 1.80GHz (Dothan) */
+static struct cpufreq_frequency_table dothan_1800[] =
+{
+ OP( 600, 988, 988, 988, 988),
+ OP( 800, 1052, 1052, 1052, 1036),
+ OP(1000, 1116, 1100, 1100, 1084),
+ OP(1200, 1164, 1164, 1148, 1132),
+ OP(1400, 1228, 1212, 1212, 1180),
+ OP(1600, 1292, 1276, 1260, 1228),
+ OP(1800, 1340, 1324, 1308, 1276),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 755 / 2.00GHz (Dothan) */
+static struct cpufreq_frequency_table dothan_2000[] =
+{
+ OP( 600, 988, 988, 988, 988),
+ OP( 800, 1052, 1036, 1036, 1036),
+ OP(1000, 1100, 1084, 1084, 1084),
+ OP(1200, 1148, 1132, 1132, 1116),
+ OP(1400, 1196, 1180, 1180, 1164),
+ OP(1600, 1244, 1228, 1228, 1196),
+ OP(1800, 1292, 1276, 1276, 1244),
+ OP(2000, 1340, 1324, 1308, 1276),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+#undef OP
+
+#define DOTHAN(cpuid, max, name) \
+{ .cpu_id = cpuid, \
+ .model_name = "Intel(R) Pentium(R) M processor " name "GHz", \
+ .max_freq = (max)*1000, \
+ .op_points = dothan_##max, \
+ .base_freq = 100000, \
+}
+
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN */
+
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA
+
+/* Intel datasheets 30526202.pdf define voltages only for highest and
+ lowest frequency modes (HFM and LFM).
+ For LFM the datasheet gives one typical voltage: LFMVccTyp.
+ For HFM the datasheet gives a min and a max voltage: HFMVccMin and HFMVccMax.
+ The tables below are using HFMVccMax for the highest frequency to be on
+ the safe side. The voltages of the intermediate frequencies are linearly
+ interpolated from LFMVccTyp and HFMVccMax as it is what I have observed
+ to be used by the ACPI tables of my laptop and of some other's one.
+
+ LFMVccTyp is 988 mv for all models
+ HFMVccMin is 1260 mv for all models
+ HFMVccMax is 1356 mv for models 730, 740, 750 and 760.
+ HFMVccMax is 1372 mv for model 770.
+ HFMVccMax is 1404 mv for model 780.
+
+ As only the first voltage of each row of the tables are used I have put
+ there the values interpolated from HFMVccMax rounded to the next higher 16 mV step
+ For reference I have put in the other 3 columns:
+ values interpolated from HFMVccMax rounded to the nearest 1 mv
+ values interpolated from HFMVccMin rounded to the next higher 16 mv step
+ values interpolated from HFMVccMin rounded to the nearest 1 mv
+*/
+
+#define OPEX(mhz, base, mva, mvb, mvc, mvd) \
+ { \
+ .frequency = (mhz) * 1000, \
+ .index = (((mhz)/(base)) << 8) | ((mva - 700) / 16) \
+ }
+
+/* Intel Pentium M processor 730 / 1.60 GHz (Sonoma) */
+static struct cpufreq_frequency_table sonoma_1596[] =
+{
+ OPEX( 798, 133, 988, 988, 988, 988),
+ OPEX(1064, 133, 1116, 1111, 1084, 1079),
+ OPEX(1330, 133, 1244, 1233, 1180, 1169),
+ OPEX(1596, 133, 1356, 1356, 1260, 1260),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 740 / 1.73 GHz (Sonoma) */
+static struct cpufreq_frequency_table sonoma_1729[] =
+{
+ OPEX( 798, 133, 988, 988, 988, 988),
+ OPEX(1064, 133, 1100, 1093, 1068, 1066),
+ OPEX(1330, 133, 1212, 1198, 1148, 1143),
+ OPEX(1729, 133, 1356, 1356, 1260, 1260),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 750 / 1.86 GHz (Sonoma) */
+static struct cpufreq_frequency_table sonoma_1862[] =
+{
+ OPEX( 798, 133, 988, 988, 988, 988),
+ OPEX(1064, 133, 1084, 1080, 1068, 1056),
+ OPEX(1330, 133, 1180, 1172, 1132, 1124),
+ OPEX(1596, 133, 1276, 1264, 1196, 1192),
+ OPEX(1862, 133, 1356, 1356, 1260, 1260),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 760 / 2.00 GHz (Sonoma) */
+static struct cpufreq_frequency_table sonoma_1995[] =
+{
+ OPEX( 798, 133, 988, 988, 988, 988),
+ OPEX(1064, 133, 1084, 1070, 1052, 1048),
+ OPEX(1330, 133, 1164, 1152, 1116, 1109),
+ OPEX(1596, 133, 1244, 1233, 1180, 1169),
+ OPEX(1995, 133, 1356, 1356, 1260, 1260),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 770 / 2.13 GHz (Sonoma) */
+static struct cpufreq_frequency_table sonoma_2128[] =
+{
+ OPEX( 798, 133, 988, 988, 988, 988),
+ OPEX(1064, 133, 1068, 1065, 1052, 1042),
+ OPEX(1330, 133, 1148, 1142, 1100, 1097),
+ OPEX(1596, 133, 1228, 1218, 1164, 1151),
+ OPEX(1862, 133, 1308, 1295, 1212, 1206),
+ OPEX(2128, 133, 1372, 1372, 1260, 1260),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+/* Intel Pentium M processor 780 / 2.26 GHz (Sonoma) */
+static struct cpufreq_frequency_table sonoma_2261[] =
+{
+ OPEX( 798, 133, 988, 988, 988, 988),
+ OPEX(1064, 133, 1068, 1064, 1052, 1037),
+ OPEX(1330, 133, 1148, 1139, 1100, 1087),
+ OPEX(1596, 133, 1228, 1215, 1148, 1136),
+ OPEX(1862, 133, 1292, 1291, 1196, 1186),
+ OPEX(2261, 133, 1404, 1404, 1260, 1260),
+ { .frequency = CPUFREQ_TABLE_END }
+};
+
+#undef OPEX
+
+#define SONOMA(cpuid, max, base, name) \
+{ .cpu_id = cpuid, \
+ .model_name = "Intel(R) Pentium(R) M processor " name "GHz", \
+ .max_freq = (max)*1000, \
+ .op_points = sonoma_##max, \
+ .base_freq = (base)*1000, \
+}
+
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA */
+
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH
+// To Do
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH */
+
+
/* CPU models, their operating frequency range, and freq/voltage
operating points */
static struct cpu_model models[] =
{
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS
+ /* Builtin tables for Banias CPUs */
_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
BANIAS(1000),
BANIAS(1100),
@@ -224,18 +457,51 @@
BANIAS(1500),
BANIAS(1600),
BANIAS(1700),
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_BANIAS */
- /* NULL model_name is a wildcard */
- { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
- { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
- { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
- { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
- { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN
+ /* Builtin tables for Dothan B0 CPUs */
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1100, "1.10"),
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1400, "1.40"),
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1500, "1.50"),
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1600, "1.60"),
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1700, "1.70"),
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 1800, "1.80"),
+ DOTHAN(&cpu_ids[CPU_DOTHAN_B0], 2000, "2.00"),
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_DOTHAN */
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA
+ /* Builtin tables for Dothan C0 CPUs, a.k.a Sonoma */
+ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1596, 133, "1.60"),
+ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1729, 133, "1.73"),
+ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1862, 133, "1.86"),
+ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 1995, 133, "2.00"),
+ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 2128, 133, "2.13"),
+ SONOMA(&cpu_ids[CPU_DOTHAN_C0], 2261, 133, "2.26"),
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_SONOMA */
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH
+ /* Builtin tables for Yonah CPUs */
+ // To Do
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN_YONAH */
+
+ /* NULL model_name is a wildcard to catch known CPU IDs for which
+ * we don't have any builtin table */
+ { &cpu_ids[CPU_BANIAS], NULL, 0, NULL, 0 },
+ { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL, 0 },
+ { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL, 0 },
+ { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL, 0 },
+ { &cpu_ids[CPU_DOTHAN_C0], NULL, 0, NULL, 0 },
+ { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL, 0 },
+ { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL, 0 },
+ /* End of the table */
{ NULL, }
};
#undef _BANIAS
#undef BANIAS
+#undef DOTHAN
+#undef SONOMA
static int centrino_cpu_init_table(struct cpufreq_policy *policy)
{
@@ -250,7 +516,7 @@
if (model->cpu_id == NULL) {
/* No match at all */
- dprintk("no support for CPU model \"%s\": "
+ dprintk(KERN_INFO PFX "no support for CPU model \"%s\": "
"send /proc/cpuinfo to " MAINTAINER "\n",
cpu->x86_model_id);
return -ENOENT;
@@ -258,10 +524,10 @@
if (model->op_points == NULL) {
/* Matched a non-match */
- dprintk("no table support for CPU model \"%s\"\n",
+ dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n",
cpu->x86_model_id);
#ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
- dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
+ dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
#endif
return -ENOENT;
}
@@ -276,7 +542,7 @@
#else
static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
-#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_BUILTIN */
static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
{
@@ -297,6 +563,13 @@
* for centrino, as some DSDTs are buggy.
* Ideally, this can be done using the acpi_data structure.
*/
+
+ if ((centrino_model[cpu]) && (centrino_model[cpu]->base_freq != 0))
+ {
+ msr = (msr >> 8) & 0xff;
+ return msr * centrino_model[cpu]->base_freq;
+ }
+
if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
(centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
(centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
@@ -348,39 +621,9 @@
return clock_freq;
}
-
#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
-static struct acpi_processor_performance *acpi_perf_data[NR_CPUS];
-
-/*
- * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States
- * library
- *
- * Before doing the actual init, we need to do _PSD related setup whenever
- * supported by the BIOS. These are handled by this early_init routine.
- */
-static int centrino_cpu_early_init_acpi(void)
-{
- unsigned int i, j;
- struct acpi_processor_performance *data;
-
- for_each_possible_cpu(i) {
- data = kzalloc(sizeof(struct acpi_processor_performance),
- GFP_KERNEL);
- if (!data) {
- for_each_possible_cpu(j) {
- kfree(acpi_perf_data[j]);
- acpi_perf_data[j] = NULL;
- }
- return (-ENOMEM);
- }
- acpi_perf_data[i] = data;
- }
-
- acpi_processor_preregister_performance(acpi_perf_data);
- return 0;
-}
+static struct acpi_processor_performance p;
/*
* centrino_cpu_init_acpi - register with ACPI P-States library
@@ -391,54 +634,50 @@
*/
static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
{
- unsigned long cur_freq;
- int result = 0, i;
- unsigned int cpu = policy->cpu;
- struct acpi_processor_performance *p;
-
- p = acpi_perf_data[cpu];
+ unsigned long cur_freq;
+ int i;
+ int result = 0;
+ unsigned int cpu = policy->cpu;
/* register with ACPI core */
- if (acpi_processor_register_performance(p, cpu)) {
- dprintk("obtaining ACPI data failed\n");
+ if (acpi_processor_register_performance(&p, cpu)) {
+ dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
return -EIO;
}
- policy->cpus = p->shared_cpu_map;
- policy->shared_type = p->shared_type;
/* verify the acpi_data */
- if (p->state_count <= 1) {
+ if (p.state_count <= 1) {
dprintk("No P-States\n");
result = -ENODEV;
goto err_unreg;
}
- if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
- (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
+ if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
+ (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
dprintk("Invalid control/status registers (%x - %x)\n",
- p->control_register.space_id, p->status_register.space_id);
+ p.control_register.space_id, p.status_register.space_id);
result = -EIO;
goto err_unreg;
}
- for (i=0; istate_count; i++) {
- if (p->states[i].control != p->states[i].status) {
+ for (i=0; istates[i].control, p->states[i].status);
+ p.states[i].control, p.states[i].status);
result = -EINVAL;
goto err_unreg;
}
- if (!p->states[i].core_frequency) {
+ if (!p.states[i].core_frequency) {
dprintk("Zero core frequency for state %u\n", i);
result = -EINVAL;
goto err_unreg;
}
- if (p->states[i].core_frequency > p->states[0].core_frequency) {
+ if (p.states[i].core_frequency > p.states[0].core_frequency) {
dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
- p->states[i].core_frequency, p->states[0].core_frequency);
- p->states[i].core_frequency = 0;
+ p.states[i].core_frequency, p.states[0].core_frequency);
+ p.states[i].core_frequency = 0;
continue;
}
}
@@ -450,26 +689,27 @@
}
centrino_model[cpu]->model_name=NULL;
- centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000;
+ centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000;
centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
- (p->state_count + 1), GFP_KERNEL);
- if (!centrino_model[cpu]->op_points) {
- result = -ENOMEM;
- goto err_kfree;
- }
-
- for (i=0; istate_count; i++) {
- centrino_model[cpu]->op_points[i].index = p->states[i].control;
- centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
+ (p.state_count + 1), GFP_KERNEL);
+ if (!centrino_model[cpu]->op_points) {
+ result = -ENOMEM;
+ goto err_kfree;
+ }
+
+ for (i=0; iop_points[i].index = p.states[i].control;
+ centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000;
dprintk("adding state %i with frequency %u and control value %04x\n",
i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
}
- centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END;
+ centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
cur_freq = get_cur_freq(cpu);
+ centrino_model[cpu]->base_freq = 0;
- for (i=0; istate_count; i++) {
- if (!p->states[i].core_frequency) {
+ for (i=0; iop_points[i].frequency = CPUFREQ_ENTRY_INVALID;
continue;
@@ -478,14 +718,14 @@
if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
(centrino_model[cpu]->op_points[i].frequency)) {
dprintk("Invalid encoded frequency (%u vs. %u)\n",
- extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
- centrino_model[cpu]->op_points[i].frequency);
+ extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
+ centrino_model[cpu]->op_points[i].frequency);
result = -EINVAL;
goto err_kfree_all;
}
if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
- p->state = i;
+ p.state = i;
}
/* notify BIOS that we exist */
@@ -498,15 +738,437 @@
err_kfree:
kfree(centrino_model[cpu]);
err_unreg:
- acpi_processor_unregister_performance(p, cpu);
- dprintk("invalid ACPI data\n");
+ acpi_processor_unregister_performance(&p, cpu);
+ dprintk(KERN_INFO PFX "invalid ACPI data\n");
return (result);
}
#else
static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
-static inline int centrino_cpu_early_init_acpi(void) { return 0; }
#endif
+static int centrino_target (struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation);
+
+
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_SYSFS
+/************************** sysfs interface for user defined voltage table ************************/
+
+static struct cpufreq_frequency_table **original_table = NULL;
+
+static void check_origial_table (unsigned int cpu)
+{
+ int i;
+
+ if (!original_table)
+ {
+ original_table = kmalloc(sizeof(struct cpufreq_frequency_table *)*NR_CPUS, GFP_KERNEL);
+ for (i=0; i < NR_CPUS; i++)
+ {
+ original_table[i] = NULL;
+ }
+ }
+
+ if (!original_table[cpu])
+ {
+ /* Count number of frequencies and allocate memory for a copy */
+ for (i=0; centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++);
+ /* Allocate memory to store the copy */
+ original_table[cpu] = (struct cpufreq_frequency_table*) kmalloc(sizeof(struct cpufreq_frequency_table)*(i+1), GFP_KERNEL);
+ /* Make copy of frequency/voltage pairs */
+ for (i=0; centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++)
+ {
+ original_table[cpu][i].frequency = centrino_model[cpu]->op_points[i].frequency;
+ original_table[cpu][i].index = centrino_model[cpu]->op_points[i].index;
+ }
+ original_table[cpu][i].frequency = CPUFREQ_TABLE_END;
+ }
+}
+
+
+static ssize_t show_user_voltage (struct cpufreq_policy *policy, char *buf)
+{
+ ssize_t bytes_written = 0;
+ unsigned int cpu = policy->cpu;
+ unsigned int op_index = 0;
+ unsigned int voltage = 0;
+
+ //dprintk("showing user voltage table in sysfs\n");
+
+ while (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ {
+ //dprintk("getting state %i \n", i);
+ voltage = centrino_model[cpu]->op_points[op_index].index;
+ voltage = 700 + ((voltage & 0xFF) << 4);
+ //dprintk("writing voltage %i: %u mV \n", i, voltage);
+ bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE, "%u",voltage);
+ op_index++;
+ if (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE, ",");
+ else
+ bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE, "\n");
+ }
+ buf[PAGE_SIZE-1] = 0;
+ return bytes_written;
+}
+
+static ssize_t
+store_user_voltage (struct cpufreq_policy *policy, const char *buf, size_t count)
+{
+ unsigned int cpu;
+ const char *curr_buf;
+ unsigned int curr_freq;
+ unsigned int op_index;
+ int isok;
+ char *next_buf;
+ unsigned int op_point;
+ ssize_t retval;
+ unsigned int voltage;
+
+ if (!policy)
+ return -ENODEV;
+ cpu = policy->cpu;
+ if (!centrino_model[cpu] || !centrino_model[cpu]->op_points)
+ return -ENODEV;
+
+ check_origial_table(cpu);
+
+ op_index = 0;
+ curr_buf = buf;
+ next_buf = NULL;
+ isok = 1;
+
+ while ((centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ && (isok))
+ {
+ voltage = simple_strtoul(curr_buf, &next_buf, 10);
+ if ((next_buf != curr_buf) && (next_buf != NULL))
+ {
+ if ((voltage >= 700) && (voltage<=1600))
+ {
+ voltage = ((voltage - 700) >> 4) & 0xFF;
+ op_point = (original_table[cpu])[op_index].index;
+ if (voltage <= (op_point & 0xFF))
+ {
+ //dprintk("setting control value %i to %04x\n", op_index, op_point);
+ op_point = (op_point & 0xFFFFFF00) | voltage;
+ centrino_model[cpu]->op_points[op_index].index = op_point;
+ }
+ else
+ {
+ op_point = (op_point & 0xFFFFFF00) | voltage;
+ dprintk("not setting control value %i to %04x because requested voltage is not lower than the default value\n", op_index, op_point);
+ //isok = 0;
+ }
+ }
+ else
+ {
+ dprintk("voltage value %i is out of bounds: %u mV\n", op_index, voltage);
+ isok = 0;
+ }
+ curr_buf = next_buf;
+ if (*curr_buf==',')
+ curr_buf++;
+ next_buf = NULL;
+ }
+ else
+ {
+ dprintk("failed to parse voltage value %i\n", op_index);
+ isok = 0;
+ }
+ op_index++;
+ }
+
+ if (isok)
+ {
+ retval = count;
+ curr_freq = cpufreq_get(policy->cpu);
+ centrino_target(policy, curr_freq, CPUFREQ_RELATION_L);
+ }
+ else
+ {
+ retval = -EINVAL;
+ }
+
+ return retval;
+}
+
+static struct freq_attr centrino_freq_attr_voltage_table =
+{
+ .attr = { .name = "voltage_table", .mode = 0644, .owner = THIS_MODULE },
+ .show = show_user_voltage,
+ .store = store_user_voltage,
+};
+
+
+static ssize_t show_user_op_points (struct cpufreq_policy *policy, char *buf)
+{
+ ssize_t bytes_written = 0;
+ unsigned int cpu = policy->cpu;
+ unsigned int op_index = 0;
+ unsigned int voltage = 0;
+ unsigned int frequency = 0;
+
+ //dprintk("showing user voltage table in sysfs\n");
+
+ while ( (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ &&(bytes_writtenop_points[op_index].index;
+ voltage = 700 + ((voltage & 0xFF) << 4);
+ frequency = centrino_model[cpu]->op_points[op_index].frequency;
+ //dprintk("writing voltage %i: %u mV \n", i, voltage);
+ bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-2, "%u:%u",frequency,voltage);
+ op_index++;
+ if (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, ",");
+ else
+ bytes_written += snprintf (&buf[bytes_written],PAGE_SIZE-bytes_written-1, "\n");
+ }
+ buf[PAGE_SIZE-1] = 0;
+ return bytes_written;
+}
+
+static ssize_t
+store_user_op_points (struct cpufreq_policy *policy, const char *buf, size_t count)
+{
+ unsigned int cpu;
+ const char *curr_buf;
+ unsigned int curr_freq;
+ unsigned int op_index;
+ unsigned int op_count;
+ int isok;
+ char *next_buf;
+ unsigned int op_point;
+ ssize_t retval;
+ unsigned int voltage;
+ unsigned int frequency;
+ int found;
+
+ if (!policy)
+ return -ENODEV;
+ cpu = policy->cpu;
+ if (!centrino_model[cpu] || !centrino_model[cpu]->op_points)
+ return -ENODEV;
+
+ check_origial_table(cpu);
+
+ op_count = 0;
+ curr_buf = buf;
+ next_buf = NULL;
+ isok = 1;
+
+ while ( (isok) && (curr_buf != NULL) )
+ {
+ op_count++;
+ // Parse frequency
+ frequency = simple_strtoul(curr_buf, &next_buf, 10);
+ if ((next_buf != curr_buf) && (next_buf != NULL))
+ {
+ // Parse separator between frequency and voltage
+ curr_buf = next_buf;
+ next_buf = NULL;
+ if (*curr_buf==':')
+ {
+ curr_buf++;
+ // Parse voltage
+ voltage = simple_strtoul(curr_buf, &next_buf, 10);
+ if ((next_buf != curr_buf) && (next_buf != NULL))
+ {
+ if ((voltage >= 700) && (voltage<=1600))
+ {
+ voltage = ((voltage - 700) >> 4) & 0xFF;
+ op_index = 0;
+ found = 0;
+ while (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ {
+ if (centrino_model[cpu]->op_points[op_index].frequency == frequency)
+ {
+ found = 1;
+ op_point = (original_table[cpu])[op_index].index;
+ if (voltage <= (op_point & 0xFF))
+ {
+ //dprintk("setting control value %i to %04x\n", op_index, op_point);
+ op_point = (op_point & 0xFFFFFF00) | voltage;
+ centrino_model[cpu]->op_points[op_index].index = op_point;
+ }
+ else
+ {
+ op_point = (op_point & 0xFFFFFF00) | voltage;
+ dprintk("not setting control value %i to %04x because requested voltage is not lower than the default value (%u MHz)\n", op_index, op_point, frequency);
+ }
+ }
+ op_index++;
+ }
+ if (found == 0)
+ {
+ dprintk("operating point # %u not found: %u MHz\n", op_count, frequency);
+ isok = 0;
+ }
+ }
+ else
+ {
+ dprintk("operating point # %u voltage value is out of bounds: %u mV\n", op_count, voltage);
+ isok = 0;
+ }
+ // Parse seprator before next operating point, if any
+ curr_buf = next_buf;
+ next_buf = NULL;
+ if (*curr_buf==',')
+ curr_buf++;
+ else
+ curr_buf = NULL;
+ }
+ else
+ {
+ dprintk("failed to parse operating point # %u voltage\n", op_count);
+ isok = 0;
+ }
+ }
+ else
+ {
+ dprintk("failed to parse operating point # %u\n", op_count);
+ isok = 0;
+ }
+ }
+ else
+ {
+ dprintk("failed to parse operating point # %u frequency\n", op_count);
+ isok = 0;
+ }
+ }
+
+ if (isok)
+ {
+ retval = count;
+ curr_freq = cpufreq_get(policy->cpu);
+ centrino_target(policy, curr_freq, CPUFREQ_RELATION_L);
+ }
+ else
+ {
+ retval = -EINVAL;
+ }
+
+ return retval;
+}
+
+static struct freq_attr centrino_freq_attr_op_points_table =
+{
+ .attr = { .name = "op_points_table", .mode = 0644, .owner = THIS_MODULE },
+ .show = show_user_op_points,
+ .store = store_user_op_points,
+};
+
+unsigned long rounded_div(unsigned long x, unsigned long y)
+{
+ return (((x*2) / y)+1)/2;
+}
+
+static ssize_t show_FSB_base_freq (struct cpufreq_policy *policy, char *buf)
+{
+ ssize_t bytes_written = 0;
+ unsigned int cpu = policy->cpu;
+ unsigned int frequency;
+ unsigned int index;
+ unsigned int op_index = 0;
+
+ frequency = centrino_model[cpu]->base_freq;
+ if (frequency!=0)
+ {
+ bytes_written += snprintf (buf, PAGE_SIZE-2, "User defined base FSB frequency:\n%u kHz\n",frequency);
+ }
+
+ bytes_written += snprintf (buf+bytes_written, PAGE_SIZE-bytes_written-2,
+ "Base FSB frequency computed from operating points table:\n");
+
+ check_origial_table(cpu);
+ while ((original_table[cpu][op_index].frequency != CPUFREQ_TABLE_END)
+ && (bytes_written < PAGE_SIZE-3))
+ {
+ index = original_table[cpu][op_index].index;
+ index = (index >> 8) & 0xFF;
+ if (index > 0)
+ {
+ frequency = rounded_div((original_table[cpu][op_index].frequency), index);
+ bytes_written += snprintf (buf+bytes_written, PAGE_SIZE-bytes_written-2, "%u kHz (%u / %u)\n",
+ frequency, original_table[cpu][op_index].frequency, index);
+ }
+ op_index++;
+ }
+
+ buf[PAGE_SIZE-1] = 0;
+ return bytes_written;
+}
+
+static ssize_t
+store_FSB_base_freq (struct cpufreq_policy *policy, const char *buf, size_t count)
+{
+ unsigned int cpu;
+ const char *curr_buf;
+ unsigned int curr_freq;
+ unsigned int frequency;
+ unsigned int index;
+ char *next_buf;
+ unsigned int op_index = 0;
+ ssize_t retval;
+
+ if (!policy)
+ return -ENODEV;
+ cpu = policy->cpu;
+ if (!centrino_model[cpu] || !centrino_model[cpu]->op_points)
+ return -ENODEV;
+
+ curr_buf = buf;
+ next_buf = NULL;
+ frequency = simple_strtoul(curr_buf, &next_buf, 10);
+ if ((next_buf != curr_buf) && (next_buf != NULL))
+ {
+ if (centrino_model[cpu]->base_freq != frequency)
+ {
+ centrino_model[cpu]->base_freq = frequency;
+
+ check_origial_table(cpu);
+ while (centrino_model[cpu]->op_points[op_index].frequency != CPUFREQ_TABLE_END)
+ {
+ if (frequency>0)
+ {
+ index = original_table[cpu][op_index].index;
+ index = (index >> 8) & 0xFF;
+ if (index > 0)
+ {
+ centrino_model[cpu]->op_points[op_index].frequency = frequency * index;
+ }
+ }
+ else
+ {
+ centrino_model[cpu]->op_points[op_index].frequency = original_table[cpu][op_index].frequency;
+ }
+ op_index++;
+ }
+ }
+
+ retval = count;
+ curr_freq = cpufreq_get(policy->cpu);
+ centrino_target(policy, curr_freq, CPUFREQ_RELATION_L);
+ }
+ else
+ {
+ retval = -EINVAL;
+ }
+
+ return retval;
+}
+
+static struct freq_attr centrino_freq_attr_FSB_Base_Freq =
+{
+ .attr = { .name = "FSB_base_frequency", .mode = 0644, .owner = THIS_MODULE },
+ .show = show_FSB_base_freq,
+ .store = store_FSB_base_freq,
+};
+
+#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_SYSFS */
+
static int centrino_cpu_init(struct cpufreq_policy *policy)
{
struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
@@ -514,13 +1176,15 @@
unsigned l, h;
int ret;
int i;
+ struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
/* Only Intel makes Enhanced Speedstep-capable CPUs */
if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
return -ENODEV;
- if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
+ if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
+ }
if (centrino_cpu_init_acpi(policy)) {
if (policy->cpu != 0)
@@ -534,7 +1198,7 @@
centrino_cpu[policy->cpu] = &cpu_ids[i];
if (!centrino_cpu[policy->cpu]) {
- dprintk("found unsupported CPU with "
+ dprintk(KERN_INFO PFX "found unsupported CPU with "
"Enhanced SpeedStep: send /proc/cpuinfo to "
MAINTAINER "\n");
return -ENODEV;
@@ -590,15 +1254,10 @@
#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
if (!centrino_model[cpu]->model_name) {
- static struct acpi_processor_performance *p;
-
- if (acpi_perf_data[cpu]) {
- p = acpi_perf_data[cpu];
- dprintk("unregistering and freeing ACPI data\n");
- acpi_processor_unregister_performance(p, cpu);
- kfree(centrino_model[cpu]->op_points);
- kfree(centrino_model[cpu]);
- }
+ dprintk("unregistering and freeing ACPI data\n");
+ acpi_processor_unregister_performance(&p, cpu);
+ kfree(centrino_model[cpu]->op_points);
+ kfree(centrino_model[cpu]);
}
#endif
@@ -632,132 +1291,72 @@
unsigned int relation)
{
unsigned int newstate = 0;
- unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
+ unsigned int msr, oldmsr, h, cpu = policy->cpu;
struct cpufreq_freqs freqs;
- cpumask_t online_policy_cpus;
cpumask_t saved_mask;
- cpumask_t set_mask;
- cpumask_t covered_cpus;
- int retval = 0;
- unsigned int j, k, first_cpu, tmp;
+ int retval;
- if (unlikely(centrino_model[cpu] == NULL))
+ if (centrino_model[cpu] == NULL)
return -ENODEV;
- if (unlikely(cpufreq_frequency_table_target(policy,
- centrino_model[cpu]->op_points,
- target_freq,
- relation,
- &newstate))) {
- return -EINVAL;
- }
-
-#ifdef CONFIG_HOTPLUG_CPU
- /* cpufreq holds the hotplug lock, so we are safe from here on */
- cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
-#else
- online_policy_cpus = policy->cpus;
-#endif
-
+ /*
+ * Support for SMP systems.
+ * Make sure we are running on the CPU that wants to change frequency
+ */
saved_mask = current->cpus_allowed;
- first_cpu = 1;
- cpus_clear(covered_cpus);
- for_each_cpu_mask(j, online_policy_cpus) {
- /*
- * Support for SMP systems.
- * Make sure we are running on CPU that wants to change freq
- */
- cpus_clear(set_mask);
- if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
- cpus_or(set_mask, set_mask, online_policy_cpus);
- else
- cpu_set(j, set_mask);
-
- set_cpus_allowed(current, set_mask);
- if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
- dprintk("couldn't limit to CPUs in this domain\n");
- retval = -EAGAIN;
- if (first_cpu) {
- /* We haven't started the transition yet. */
- goto migrate_end;
- }
- break;
- }
-
- msr = centrino_model[cpu]->op_points[newstate].index;
+ set_cpus_allowed(current, policy->cpus);
+ if (!cpu_isset(smp_processor_id(), policy->cpus)) {
+ dprintk("couldn't limit to CPUs in this domain\n");
+ return(-EAGAIN);
+ }
- if (first_cpu) {
- rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
- if (msr == (oldmsr & 0xffff)) {
- dprintk("no change needed - msr was and needs "
- "to be %x\n", oldmsr);
- retval = 0;
- goto migrate_end;
- }
+ if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq,
+ relation, &newstate)) {
+ retval = -EINVAL;
+ goto migrate_end;
+ }
- freqs.old = extract_clock(oldmsr, cpu, 0);
- freqs.new = extract_clock(msr, cpu, 0);
+ msr = centrino_model[cpu]->op_points[newstate].index;
+ rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
- dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
- target_freq, freqs.old, freqs.new, msr);
+ if (msr == (oldmsr & 0xffff)) {
+ retval = 0;
+ dprintk("no change needed - msr was and needs to be %x\n", oldmsr);
+ goto migrate_end;
+ }
- for_each_cpu_mask(k, online_policy_cpus) {
- freqs.cpu = k;
- cpufreq_notify_transition(&freqs,
- CPUFREQ_PRECHANGE);
- }
+ freqs.cpu = cpu;
+ freqs.old = extract_clock(oldmsr, cpu, 0);
+ freqs.new = extract_clock(msr, cpu, 0);
- first_cpu = 0;
- /* all but 16 LSB are reserved, treat them with care */
- oldmsr &= ~0xffff;
- msr &= 0xffff;
- oldmsr |= msr;
- }
+ dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
+ target_freq, freqs.old, freqs.new, msr);
- wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
- if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
- break;
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- cpu_set(j, covered_cpus);
- }
+ /* all but 16 LSB are "reserved", so treat them with
+ care */
+ oldmsr &= ~0xffff;
+ msr &= 0xffff;
+ oldmsr |= msr;
- for_each_cpu_mask(k, online_policy_cpus) {
- freqs.cpu = k;
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- }
+ wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
- if (unlikely(retval)) {
- /*
- * We have failed halfway through the frequency change.
- * We have sent callbacks to policy->cpus and
- * MSRs have already been written on coverd_cpus.
- * Best effort undo..
- */
-
- if (!cpus_empty(covered_cpus)) {
- for_each_cpu_mask(j, covered_cpus) {
- set_cpus_allowed(current, cpumask_of_cpu(j));
- wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
- }
- }
-
- tmp = freqs.new;
- freqs.new = freqs.old;
- freqs.old = tmp;
- for_each_cpu_mask(j, online_policy_cpus) {
- freqs.cpu = j;
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- }
- }
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ retval = 0;
migrate_end:
set_cpus_allowed(current, saved_mask);
- return 0;
+ return (retval);
}
static struct freq_attr* centrino_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
+#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_SYSFS
+ ¢rino_freq_attr_voltage_table,
+ ¢rino_freq_attr_op_points_table,
+ ¢rino_freq_attr_FSB_Base_Freq,
+#endif
NULL,
};
@@ -795,25 +1394,12 @@
if (!cpu_has(cpu, X86_FEATURE_EST))
return -ENODEV;
- centrino_cpu_early_init_acpi();
-
return cpufreq_register_driver(¢rino_driver);
}
static void __exit centrino_exit(void)
{
-#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
- unsigned int j;
-#endif
-
cpufreq_unregister_driver(¢rino_driver);
-
-#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
- for_each_possible_cpu(j) {
- kfree(acpi_perf_data[j]);
- acpi_perf_data[j] = NULL;
- }
-#endif
}
MODULE_AUTHOR ("Jeremy Fitzhardinge ");
@@ -822,3 +1408,4 @@
late_initcall(centrino_init);
module_exit(centrino_exit);
+